module regCC (
    /*AUTOARG*/
   // Outputs
   cc,
   // Inputs
   clock, reset, alucc, setcc
   );

input           clock;
input           reset;
input   [2:0]   alucc; 
input           setcc;
output  [2:0]   cc;

/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [2:0]               cc;
// End of automatics
always @(posedge clock, posedge reset) begin
    if(reset) begin
        cc <= 3'b100;
    end else if(setcc) begin
        cc <= alucc;
    end
end

endmodule

